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statemachine11.2
- 推荐下载,verilog状态机实例.体现了流水线思想的应用 -recommend downloading Verilog state machine example. Pipeline reflects the thinking of the application
8.10
- 强烈推荐下载,verilog状态机实例.可以在modelsim下运行. -strongly recommend downloading Verilog state machine example. In modelsim running.
washmachine
- 在MAXPULS II环境下，采用Verilog开发的自动洗衣机的控制程序,在MAXPULS下可以直接通过编译-in MAXPULS II environment, using Verilog development of the automatic washing machine control procedures, the MAXPULS can be directly through the compiler
xcv
- verilog编写的状态机检测00100序列. 实现 input:...011000010010000... output:...000000000100100... 并且 用测试模块来验证状态是否正确工作-verilog prepared by the state machine detected 00,100 sequences. Achieve input : ... ... 011000010010000 output : 000000000100100 ... ... a
16bit_booth_multiplier_STG
- verilog程序，实现两个16bit数乘法，采用booth算法，基于状态机实现，分层次为datapath和controller两个子模块，testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-mo
Verilog_Development_Board_Sources
- 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Development Board VHDL source code q
9.7_DIRIVER_control
- 基于Verilog-HDL的硬件电路的实现 9.7 步进电机的控制 9.7.1 步进电机驱动的逻辑符号 9.7.2 步进电机驱动的时序图 9.7.3 步进电机驱动的逻辑框图 9.7.4 计数模块的设计与实现 9.7.5 译码模块的设计与实现 9.7.6 步进电机驱动的Verilog-HDL描述 9.7.7 编译指令-\"宏替换`define\"的使用方法 9.7.8 编译指令-\"时间尺度`timescale
03034
- verilog中的一个不用状态机和决断函数就可以实现多重函数赋值的例子，希望对你用帮助。-verilog of a state machine and no decisive function could achieve multiple functions assigned to the case, you want to help.
SDRAM
- verilog语言对SDRAM读写时序的描述，采用状态机结构实现的读写功能-timing of the SDRAM read and write verilog language descr iption, a state machine structure to achieve read and write capabilities
xujiance
- 设计一个序检测电路，功能是检测出串行输入数据Data中的4位二进制序列1101（自左至右输入），当检测到该序列时，输出Out为1；没有检测到该序列时，输出输出Out为0，要求： （1）用状态机方法设计； （2）用Verilog HDL语言设计，用Modelsim软件做功能仿真。(A sequence detection circuit is designed to detect the 4 bit binary sequence 1101 in the serial input data D
14_ethernet_test
- 千兆网学习代码 ISE，状态机实现数据打包，基于PHY芯片实现数据传输(ethernet communication sample with verilog,state machine)
eda
- 在Verilog HDL中使用任务（task）， 利用有限状态机进行时序逻辑的设计，利用SRAM设计一个LIFO(In Verilog HDL, the task (task) is used, the finite state machine is used to design the time series logic, and a LIFO is designed by SRAM)
lession_10 led_diver
- 流水灯驱动 状态机写的 很好 已经运用有实际编程中(LED drive The state machine is well written and has been used in practical programming)
uart
- 用verilog实现UART串口收发。状态机形式实现，波特率可调(Use verilog to achieve UART serial transceiver. State machine form, adjustable baud rate)
UART发送接收奇偶校验
- 状态机，串口收发，以及奇偶校验。 even_parity.v奇偶校验； receive_byte.v字节接收； send_byte.v字节发送(state machine,UART even_parity.v even parity; receive_byte.v receiving byte; send_byte.v sending byte)
autosell
- 基于FPGA的自动售货机，有两种商品，每种都是1.5元，可以投入1元和五角两种货币。(A vending machine based on FPGA,)
4bit_mealy
- Mealy machine is a state machine whose output is determined by the current state and the current inputs.
4bit_moore
- Moore machine is state machine whose output is a function of only the current state.
vendor
- 售货机的verilog模块设计及测试，简单状态机。(Verilog module design and test of vending machine, simple state machine.)
new.v
- 状态机写的axi slave，模式较少，基本功能齐全，轻便,仿真综合通过(AXI4 slave programmed by state machine approach)